參數資料
型號: MPC8548EHXAUJ
廠商: Freescale Semiconductor
文件頁數: 62/151頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC III 783-FCCBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,FCBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
18
Freescale Semiconductor
Input Clocks
4.5
Platform to FIFO Restrictions
Note the following FIFO maximum speed restrictions based on platform speed.
For FIFO GMII mode:
FIFO TX/RX clock frequency
platform clock frequency/4.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency must be no more
than 127 MHz.
For FIFO encoded mode:
FIFO TX/RX clock frequency
platform clock frequency/4.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency must be no more
than 167 MHz.
4.6
Platform Frequency Requirements for PCI-Express and Serial
RapidIO
The CCB clock frequency must be considered for proper operation of the high-speed PCI-Express and
Serial RapidIO interfaces as described below.
For proper PCI Express operation, the CCB clock frequency must be greater than:
527 MHz
(PCI-Express link width)
8
See MPC8548ERM, Rev. 2, PowerQUICC III Integrated Processor Family Reference Manual,
Section 18.1.3.2, “Link Width,” for PCI Express interface width details.
For proper serial RapidIO operation, the CCB clock frequency must be greater than:
2
(0.80) (Serial RapidIO interface frequency) × (Serial RapidIO link width)
64
See MPC8548ERM, Rev. 2, PowerQUICC III Integrated Processor Family Reference Manual,
Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency
details.
4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform see the specific section of
this document.
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