
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
124
Freescale Semiconductor
Package Description
LSYNC_IN
F27
I
BVDD
—
LSYNC_OUT
F28
O
BVDD
—
DMA
DMA_DACK[0:1]
AD3, AE1
O
OVDD
5, 9, 108
DMA_DREQ[0:1]
AD4, AE2
I
OVDD
—
DMA_DDONE[0:1]
AD2, AD1
O
OVDD
—
Programmable Interrupt Controller
UDE
AH16
I
OVDD
—
MCP
AG19
I
OVDD
—
IRQ[0:7]
AG23, AF18, AE18, AF20, AG18, AF17, AH24,
AE20
IOVDD
—
IRQ[8]
AF19
I
OVDD
—
IRQ[9]/DMA_DREQ3
AF21
I
OVDD
1
IRQ[10]/DMA_DACK3
AE19
I/O
OVDD
1
IRQ[11]/DMA_DDONE3
AD20
I/O
OVDD
1
IRQ_OUT
AD18
O
OVDD
2, 4
Ethernet Management Interface
EC_MDC
AB9
O
OVDD
5, 9
EC_MDIO
AC8
I/O
OVDD
—
Gigabit Reference Clock
EC_GTX_CLK125
V11
I
LVDD
—
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_RXD[7:0]
R5, U1, R3, U2, V3, V1, T3, T2
I
LVDD
—
TSEC1_TXD[7:0]
T10, V7, U10, U5, U4, V6, T5, T8
O
LVDD
5, 9
TSEC1_COL
R4
I
LVDD
—
TSEC1_CRS
V5
I/O
LVDD
20
TSEC1_GTX_CLK
U7
O
LVDD
—
TSEC1_RX_CLK
U3
I
LVDD
—
TSEC1_RX_DV
V2
I
LVDD
—
TSEC1_RX_ER
T1
I
LVDD
—
TSEC1_TX_CLK
T6
I
LVDD
—
TSEC1_TX_EN
U9
O
LVDD
30
TSEC1_TX_ER
T7
O
LVDD
—
GPIN[0:7]
P2, R2, N1, N2, P3, M2, M1, N3
I
LVDD
103
Table 74. MPC8543E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes