• 參數(shù)資料
    型號(hào): MPC8548ECVUAQHA
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
    文件頁數(shù): 77/142頁
    文件大小: 1504K
    代理商: MPC8548ECVUAQHA
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    4
    Freescale Semiconductor
    Overview
    – Up to 32 simultaneous open pages for DDR2
    — Contiguous or discontiguous memory mapping
    — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
    transactions
    — Sleep mode support for self-refresh SDRAM
    — On-die termination support when using DDR2
    — Supports auto refreshing
    — On-the-fly power management using CKE signal
    — Registered DIMM support
    — Fast memory access via JTAG port
    — 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)
    — Support for battery-backed main memory
    Programmable interrupt controller (PIC)
    — Programming model is compliant with the OpenPIC architecture.
    — Supports 16 programmable interrupt and processor task priority levels
    — Supports 12 discrete external interrupts
    — Supports 4 message interrupts with 32-bit messages
    — Supports connection of an external interrupt controller such as the 8259 programmable
    interrupt controller
    — Four global high resolution timers/counters that can generate interrupts
    — Supports a variety of other internal interrupt sources
    — Supports fully nested interrupt delivery
    — Interrupts can be routed to external pin for external processing.
    — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
    — Interrupt summary registers allow fast identification of interrupt source.
    Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
    IKE, WTLS/WAP, SSL/TLS, and 3GPP
    — Four crypto-channels, each supporting multi-command descriptor chains
    Dynamic assignment of crypto-execution units via an integrated controller
    Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
    — PKEU—public key execution unit
    – RSA and Diffie-Hellman; programmable field size up to 2048 bits
    – Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to
    511 bits
    — DEU—Data Encryption Standard execution unit
    – DES, 3DES
    – Two key (K1, K2) or three key (K1, K2, K3)
    – ECB and CBC modes for both DES and 3DES
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