參數(shù)資料
型號(hào): MPC8548ECPXAUJB
廠商: Freescale Semiconductor
文件頁數(shù): 101/151頁
文件大小: 0K
描述: MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
53
Programmable Interrupt Controller
11
Programmable Interrupt Controller
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed
polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods).
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the device.
12.1
JTAG DC Electrical Characteristics
This table provides the DC electrical characteristics for the JTAG interface.
12.2
JTAG AC Electrical Specifications
This table provides the JTAG AC timing specifications as defined in Figure 30 through Figure 32.
Table 43. JTAG DC Electrical Characteristics
Parameter
Symbol1
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current (VIN
1 = 0 V or V
IN = VDD)IIN
—±5
A
High-level output voltage (OVDD = min, IOH = –2 mA)
VOH
2.4
V
Low-level output voltage (OVDD = min, IOL = 2 mA)
VOL
—0.4
V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN.
Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)1
Parameter
Symbol2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
033.3
MHz
JTAG external clock cycle time
t JTG
30
ns
JTAG external clock pulse width measured at 1.4 V
tJTKHKL
15
ns
JTAG external clock rise and fall times
tJTGR & tJTGF
02
ns
6
TRST assert time
tTRST
25
ns
3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
0
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
20
25
ns
4
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