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    參數(shù)資料
    型號: MPC8548ECHXAVJA
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, CERAMIC, BGA-783
    文件頁數(shù): 35/142頁
    文件大小: 1504K
    代理商: MPC8548ECHXAVJA
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    Freescale Semiconductor
    13
    Electrical Characteristics
    2.1.3
    Output Driver Characteristics
    Table 3 provides information on the characteristics of the output driver strengths. The values are
    preliminary estimates.
    2.2
    Power Sequencing
    The device requires its power rails to be applied in a specific sequence in order to ensure proper device
    operation. These requirements are as follows for power-up:
    1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD
    2. GVDD
    All supplies must be at their stable values within 50 ms.
    NOTE
    Items on the same line have no ordering requirement with respect to one
    another. Items on separate lines must be ordered sequentially such that
    voltage rails on a previous step must reach 90% of their value before the
    voltage rails on the current step reach 10% of theirs.
    Table 3. Output Drive Capability
    Driver Type
    Programmable
    Output Impedance
    (
    Ω)
    Supply
    Voltage
    Notes
    Local bus interface utilities signals
    25
    BVDD = 3.3 V
    BVDD = 2.5 V
    1
    45(default)
    BVDD = 3.3 V
    BVDD = 2.5 V
    PCI signals
    25
    OVDD = 3.3 V
    2
    45(default)
    DDR signal
    18
    36 (half strength mode)
    GVDD = 2.5 V
    3
    DDR2 signal
    18
    36 (half strength mode)
    GVDD = 1.8 V
    3
    TSEC/10/100 signals
    45
    L/TVDD = 2.5/3.3 V
    DUART, system control, JTAG
    45
    OVDD = 3.3 V
    I2C
    150
    OVDD = 3.3 V
    Notes:
    1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
    2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
    3. The drive strength of the DDR interface in half-strength mode is at Tj = 105°C and at GVDD (min).
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