參數(shù)資料
    型號: MPC8548CVTATJB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, PLASTIC, BGA-783
    文件頁數(shù): 118/142頁
    文件大小: 1504K
    代理商: MPC8548CVTATJB
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    Freescale Semiconductor
    77
    Serial RapidIO
    17.3
    Signal Definitions
    LP-serial links use differential signaling. This section defines terms used in the description and
    specification of differential signals. Figure 51 shows how the signals are defined. The figures show
    waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal
    swings between A volts and B volts where A > B. Using these waveforms, the definitions are as follows:
    1. The transmitter output signals and the receiver input signals TD, TD, RD, and RD each have a
    peak-to-peak swing of A – B volts.
    2. The differential output signal of the transmitter, VOD, is defined as VTD –VTD.
    3. The differential input signal of the receiver, VID, is defined as VRD –VRD.
    4. The differential output signal of the transmitter and the differential input signal of the receiver
    each range from A – B to –(A – B) volts.
    5. The peak value of the differential transmitter output signal and the differential receiver input
    signal is A – B volts.
    6. The peak-to-peak value of the differential transmitter output signal and the differential receiver
    input signal is 2
    × (A – B) volts.
    Figure 51. Differential Peak–Peak Voltage of Transmitter or Receiver
    To illustrate these definitions using real values, consider the case of a CML (current mode logic)
    transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
    that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of the signals TD and
    TD is 500 mVp-p. The differential output signal ranges between 500 and –500 mV. The peak differential
    voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVp-p.
    17.4
    Equalization
    With the use of high speed serial links, the interconnect media will cause degradation of the signal at the
    receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss
    can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.
    To negate a portion of these effects, equalization can be used. The most common equalization techniques
    that can be used are:
    A passive high pass filter network placed at the receiver. This is often referred to as passive
    equalization.
    The use of active circuits in the receiver. This is often referred to as adaptive equalization.
    Differential Peak-to-Peak = 2
    × (A – B)
    A Volts
    TD or RD
    B Volts
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