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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MPC8547EVTAQGB |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 128/151闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MPU POWERQUICC III 783-PBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | MPC85xx |
| 铏曠悊鍣ㄩ鍨嬶細 | 32-浣� MPC85xx PowerQUICC III |
| 閫熷害锛� | 1.0GHz |
| 闆诲锛� | 1.1V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 783-BBGA锛孎(xi脿n)CBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 783-FCPBGA锛�29x29锛� |
| 鍖呰锛� | 鎵樼洡 |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
78
Freescale Semiconductor
PCI Express
VRX-CM-ACp
AC peak
common mode
input voltage
鈥斺€�
150
mV
VRX-CM-ACp = |VRXD+ 鈥� VRXD-|/2 + VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D鈥�| 2.
See Note 2.
RLRX-DIFF
Differential
return loss
15
鈥�
dB
Measured over 50 MHz to 1.25 GHz with the D+
and D鈥� lines biased at +300 mV and 鈥�300 mV,
respectively. See Note 4.
RLRX-CM
Common mode
return loss
6
鈥�
dB
Measured over 50 MHz to 1.25 GHz with the D+
and D鈥� lines biased at 0 V. See Note 4.
ZRX-DIFF-DC
DC differential
input impedance
80
100
120
RX DC differential mode impedance. See Note 5.
ZRX-DC
DC input
impedance
40
50
60
Required RX D+ as well as D鈥� DC impedance
(50 卤 20% tolerance). See Notes 2 and 5.
ZRX-HIGH-IMP-DC
Powered down
DC input
impedance
200 k
鈥�
Required RX D+ as well as D鈥� DC impedance
when the receiver terminations do not have
power. See Note 6.
VRX-IDLE-DET-DIFFp-p
Electrical idle
detect threshold
65
鈥�
175
mV
VRX-IDLE-DET-DIFFp-p = 2 脳 |VRX-D+ 鈥揤RX-D鈥�|.
Measured at the package pins of the receiver
TRX-IDLE-DET-DIFF-
ENTERTIME
Unexpected
electrical idle
enter detect
threshold
integration time
鈥�
10
ms
An unexpected electrical idle (VRX-DIFFp-p <
VRX-IDLE-DET-DIFFp-p) must be recognized no
longer than TRX-IDLE-DET-DIFF-ENTERING to signal
an unexpected idle condition.
Table 57. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Unit
Comments
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| MPC8547EVTAQGD | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU PQ38 ST WE 1000 R3.0 RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
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