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鍨嬭櫉锛� MPC8547EVTAQGB
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鎻忚堪锛� MPU POWERQUICC III 783-PBGA
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绯诲垪锛� MPC85xx
铏曠悊鍣ㄩ鍨嬶細 32-浣� MPC85xx PowerQUICC III
閫熷害锛� 1.0GHz
闆诲锛� 1.1V
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灏佽/澶栨锛� 783-BBGA锛孎(xi脿n)CBGA
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鍖呰锛� 鎵樼洡
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
78
Freescale Semiconductor
PCI Express
VRX-CM-ACp
AC peak
common mode
input voltage
鈥斺€�
150
mV
VRX-CM-ACp = |VRXD+ 鈥� VRXD-|/2 + VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D鈥�| 2.
See Note 2.
RLRX-DIFF
Differential
return loss
15
鈥�
dB
Measured over 50 MHz to 1.25 GHz with the D+
and D鈥� lines biased at +300 mV and 鈥�300 mV,
respectively. See Note 4.
RLRX-CM
Common mode
return loss
6
鈥�
dB
Measured over 50 MHz to 1.25 GHz with the D+
and D鈥� lines biased at 0 V. See Note 4.
ZRX-DIFF-DC
DC differential
input impedance
80
100
120
RX DC differential mode impedance. See Note 5.
ZRX-DC
DC input
impedance
40
50
60
Required RX D+ as well as D鈥� DC impedance
(50 卤 20% tolerance). See Notes 2 and 5.
ZRX-HIGH-IMP-DC
Powered down
DC input
impedance
200 k
鈥�
Required RX D+ as well as D鈥� DC impedance
when the receiver terminations do not have
power. See Note 6.
VRX-IDLE-DET-DIFFp-p
Electrical idle
detect threshold
65
鈥�
175
mV
VRX-IDLE-DET-DIFFp-p = 2 脳 |VRX-D+ 鈥揤RX-D鈥�|.
Measured at the package pins of the receiver
TRX-IDLE-DET-DIFF-
ENTERTIME
Unexpected
electrical idle
enter detect
threshold
integration time
鈥�
10
ms
An unexpected electrical idle (VRX-DIFFp-p <
VRX-IDLE-DET-DIFFp-p) must be recognized no
longer than TRX-IDLE-DET-DIFF-ENTERING to signal
an unexpected idle condition.
Table 57. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Unit
Comments
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