參數資料
型號: MPC8547ECPXAQGB
廠商: Freescale Semiconductor
文件頁數: 51/151頁
文件大小: 0K
描述: MPU POWERQUICC III 783-PBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,FCBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
144
Freescale Semiconductor
System Design Information
SD_REF_CLK
NOTE
It is recommended to power down the unused lane through SRDSCR1[0:7]
register (offset = 0xE_0F08) (this prevents the oscillations and holds the
receiver output in a fixed state) that maps to SERDES lane 0 to lane 7
accordingly.
Pins V28 and M26 must be tied to XVDD. Pins V27 and M25 must be tied to GND through a 300-
resistor.
22.11 Guideline for PCI Interface Termination
PCI termination if PCI 1 or PCI 2 is not used at all.
Option 1
If PCI arbiter is enabled during POR:
All AD pins are driven to the stable states after POR. Therefore, all ADs pins can be floating.
All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor.
It is optional to disable PCI block through DEVDISR register after POR reset.
Option 2
If PCI arbiter is disabled during POR:
All AD pins are in the input state. Therefore, all ADs pins need to be grouped together and tied to
OVDD through a single (or multiple) 10-k resistor(s).
All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor.
It is optional to disable PCI block through DEVDISR register after POR reset.
22.12 Guideline for LBIU Termination
If the LBIU parity pins are not used, the following is the termination recommendation:
For LDP[0:3]—tie them to ground or the power supply rail via a 4.7-k
resistor.
For LPBSE—tie it to the power supply rail via a 4.7-k
resistor (pull-up resistor).
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