
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
34
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC)
Figure 14 shows the TBI transmit AC timing diagram.
Figure 14. TBI Transmit AC Timing Diagram
8.2.4.2
TBI Receive AC Timing Specifications
Table 31 provides the TBI receive AC timing specifications.
Table 31. TBI Receive AC Timing Specifications
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
TSEC
n_RX_CLK[0:1] clock period
tTRX
—
16.0
—
ns
TSEC
n_RX_CLK[0:1] skew
tSKTRX
7.5
—
8.5
ns
TSEC
n_RX_CLK[0:1] duty cycle
tTRXH/tTRX
40
—
60
%
RCG[9:0] setup time to rising TSEC
n_RX_CLK
tTRDVKH
2.5
—
ns
RCG[9:0] hold time to rising TSEC
n_RX_CLK
tTRDXKH
1.5
—
ns
TSEC
n_RX_CLK[0:1] clock rise time (20%–80%)
tTRXR
2
0.7
—
2.4
ns
TSEC
n_RX_CLK[0:1] clock fall time (80%–20%)
tTRXF
2
0.7
—
2.4
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K)
going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input
signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that
is being skewed (TRX).
2. Guaranteed by design.
GTX_CLK
TCG[9:0]
tTTXR
tTTX
tTTXH
tTTXR
tTTXF
tTTKHDV
tTTKHDX
tTTXF