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    • 參數(shù)資料
      型號: MPC8545EHXATG
      廠商: Freescale Semiconductor
      文件頁數(shù): 134/151頁
      文件大小: 0K
      描述: IC MPU PWRQUICC III 783-FCCBGA
      標準包裝: 1
      系列: MPC85xx
      處理器類型: 32-位 MPC85xx PowerQUICC III
      速度: 1.2GHz
      電壓: 1.1V
      安裝類型: 表面貼裝
      封裝/外殼: 783-BBGA,F(xiàn)CBGA
      供應商設備封裝: 783-FCPBGA(29x29)
      包裝: 托盤
      MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
      Freescale Semiconductor
      83
      Serial RapidIO
      18.5
      Explanatory Note on Transmitter and Receiver Specifications
      AC electrical specifications are given for transmitter and receiver. Long- and short-run interfaces at three
      baud rates (a total of six cases) are described.
      The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
      in Clause 47 of IEEE 802.3ae-2002.
      XAUI has similar application goals to Serial RapidIO, as described in Section 8.1. The goal of this
      standard is that electrical designs for Serial RapidIO can reuse electrical designs for XAUI, suitably
      modified for applications at the baud intervals and reaches described herein.
      18.6
      Transmitter Specifications
      LP-serial transmitter electrical and timing specifications are stated in the text and tables of this section.
      The differential return loss, S11, of the transmitter in each case shall be better than:
      –10 dB for (baud frequency)/10 < Freq(f) < 625 MHz, and
      –10 dB + 10log(f/625 MHz) dB for 625 MHz
      Freq(f) baud frequency
      The reference impedance for the differential return loss measurements is 100-
      resistive. Differential
      return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components
      related to the driver. The output impedance requirement applies to all valid output levels.
      It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output,
      in each case have a minimum value 60 ps.
      It is recommended that the timing skew at the output of an LP-serial transmitter between the two signals
      that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.
      Table 59. Short Run Transmitter AC Timing Specifications—1.25 GBaud
      Characteristic
      Symbol
      Range
      Unit
      Notes
      Min
      Max
      Output voltage
      VO
      –0.40
      2.30
      V
      Voltage relative to COMMON of either signal
      comprising a differential pair
      Differential output voltage
      VDIFFPP
      500
      1000
      mV p-p
      Deterministic jitter
      JD
      —0.17
      UI p-p
      Total jitter
      JT
      —0.35
      UI p-p
      Multiple output skew
      SMO
      1000
      ps
      Skew at the transmitter output between lanes of a
      multilane link
      Unit Interval
      UI
      800
      ps
      ±100 ppm
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