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參數資料
| 型號： | MPC8544VTARJA |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 9/117頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCBGA |
| 標準包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.067GHz |
| 電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，FCBGA |
| 供應商設備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
106
Freescale Semiconductor
System Design Information
21.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS, respectively). The AVDD
level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 65, one to each of the
AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of 783 FC-PBGA the footprint, without the inductance of vias.
Figure 65 shows the PLL power supply filter circuit.
Figure 65. MPC8544E PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
Figure 66. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be
near the AVDD_SRDSn balls. The 0.003-F capacitor is closest to the balls, followed by the 1-F capacitor,
and finally the 1-
Ωresistor to the board supply plane. The capacitors are connected from AV
DD_SRDSn
to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All
traces should be kept short, wide, and direct.
Figure 66. SerDes PLL Power Supply Filter Circuit
VDD
AVDD
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
2.2 F1
0.003 F
GND
1.0
Ω
AVDD_SRDS
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
SVDD
2.2 F1
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