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    參數(shù)資料
    型號： MPC8544VTALFA
    廠商： Freescale Semiconductor
    文件頁數(shù)： 71/117頁
    文件大小： 0K
    描述： IC MPU POWERQUICC III 783-FCBGA
    標準包裝： 36
    系列： MPC85xx
    處理器類型： 32-位 MPC85xx PowerQUICC III
    速度： 667MHz
    電壓： 0.95 V ~ 1.05 V
    安裝類型： 表面貼裝
    封裝/外殼： 783-BBGA，F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
    包裝： 托盤
    MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
    Freescale Semiconductor
    57
    JTAG
    Figure 34 provides the AC test load for TDO and the boundary-scan outputs.
    Figure 34. AC Test Load for the JTAG Interface
    Figure 35 provides the JTAG clock input timing diagram.
    Figure 35. JTAG Clock Input Timing Diagram
    Figure 36 provides the TRST timing diagram.
    Figure 36. TRST Timing Diagram
    JTAG external clock to output high impedance:
    Boundary-scan data
    TDO
    tJTKLDZ
    tJTKLOZ
    3
    19
    9
    ns
    5
    Notes:
    1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
    The output timings are measured at the pins. All output timings assume a purely resistive 50-
    Ω load (see Figure 34).
    Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
    2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
    inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
    timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
    going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
    (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
    symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
    latter convention is used with the appropriate letter: R (rise) or F (fall).
    3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
    4. Non-JTAG signal input timing with respect to tTCLK.
    5. Non-JTAG signal output timing with respect to tTCLK.
    Table 50. JTAG AC Timing Specifications (Independent of SYSCLK)1 (continued)
    At recommended operating conditions (see Table 3).
    Parameter
    Symbol2
    Min
    Max
    Unit
    Notes
    Output
    Z0 = 50 Ω
    OVDD/2
    RL = 50 Ω
    JTAG
    tJTKHKL
    tJTGR
    External Clock
    VM
    tJTG
    tJTGF
    VM = Midpoint Voltage (OVDD/2)
    TRST
    VM = Midpoint Voltage (OVDD/2)
    VM
    tTRST
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    MPC8544VTAQGA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC PQ38K 8544 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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