參數(shù)資料
型號： MPC8544EVTALFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 94/120頁
文件大?。?/td> 1321K
代理商： MPC8544EVTALFB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
75
PCI Express
17.2
AC Requirements for PCI Express SerDes Clocks
Table 58 provides the AC requirements for the PCI Express SerDes clocks.
17.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
17.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please refer to the
PCI Express Base Specification. Rev. 1.0a.
17.4.1
Differential Transmitter (TX) Output
Table 59 defines the specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 58. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol2
Parameter Description
Min
Typ
Max
Units
Notes
tREF
REFCLK cycle time
—
10
—
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles
——
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to
mean edge location
–50
—
50
ps
—
Notes:
1. Typical based on
PCI Express Specification 2.0.
2. Guaranteed by characterization.
Table 59. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Nom
Max
Unit
Comments
UI
Unit interval
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for Spread Spectrum Clock
dictated variations. See Note 1.
VTX-DIFFp-p
Differential peak-to-
peak output voltage
0.8
—
1.2
V
VTX-DIFFp-p = 2*|VTX-D+ – VTX-D–|.
See Note 2.
VTX-DE-RATIO
De- emphasized
differential output
voltage (ratio)
–3.0
–3.5
–4.0
dB
Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by
the VTX-DIFFp-p of the first bit after a
transition. See Note 2.
TTX-EYE
Minimum TX eye width
0.70
—
UI
The maximum transmitter jitter can be
derived as TTX-MAX-JITTER = 1 – TTX-EYE
= 0.3 UI. See Notes 2 and 3.
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