參數(shù)資料
型號(hào): MPC8544CVTARGB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1067 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù): 32/120頁
文件大?。?/td> 1321K
代理商: MPC8544CVTARGB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
19
DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 15 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8 V.
Table 16 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.
Table 17 provides the input AC timing specifications for the DDR SDRAM interface.
Table 15. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
V
Table 16. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
V
Table 17. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MECC/MDM
tCISKEW
ps
1, 2
533 MHz
–300
300
3
400 MHz
–365
365
333 MHz
–390
390
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ± (T/4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW. See Figure 3.
3. Maximum DDR1 frequency is 400 MHz.
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