參數(shù)資料
型號： MPC8544AVTAQG
廠商： Freescale Semiconductor
文件頁數(shù)： 25/117頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
配用： MPC8544DS-ND - BOARD DEVELOPMENT SYSTEM 8544
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
15
Input Clocks
4.2
Real-Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal should be greater than 2 × the period of the
CCB clock. That is, minimum clock high time is 2
× t
CCB, and minimum clock low time is 2 × tCCB. There
is no minimum RTC frequency; RTC may be grounded if not needed.
4.3
eTSEC Gigabit Reference Clock Timing
Table 7 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for
the MPC8544E.
4.4
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed.
For FIFO GMII mode:
FIFO TX/RX clock frequency
≤platform clock frequency ÷ 4.2
For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more
than 127 MHz.
For FIFO encoded mode:
FIFO TX/RX clock frequency
≤platform clock frequency ÷ 3.2
For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more
than 167 MHz.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
EC_GTX_CLK125 frequency
fG125
—125
—
MHz
—
EC_GTX_CLK125 cycle time
tG125
—8—
ns
—
EC_GTX_CLK rise and fall time
LVDD, TVDD = 2.5 V
LVDD, TVDD = 3.3 V
tG125R/tG125F
——
0.75
1.0
ns
1
EC_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
—
55
53
%2
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7 V for
L/TVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty
cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.7.4, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T
reference clock.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8544AVTAQGA 制造商:Freescale Semiconductor 功能描述:PQ38K 8544 - Bulk
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