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  • 參數(shù)資料
    型號(hào): MPC8543EVUANG
    廠商: Freescale Semiconductor
    文件頁數(shù): 97/151頁
    文件大?。?/td> 0K
    描述: IC MPU PWRQUICC III 783-FCCBGA
    標(biāo)準(zhǔn)包裝: 1
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 800MHz
    電壓: 1.1V
    安裝類型: 表面貼裝
    封裝/外殼: 783-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
    包裝: 托盤
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
    Freescale Semiconductor
    5
    Overview
    — AESU—Advanced Encryption Standard unit
    – Implements the Rijndael symmetric key cipher
    – ECB, CBC, CTR, and CCM modes
    – 128-, 192-, and 256-bit key lengths
    — AFEU—ARC four execution unit
    Implements a stream cipher compatible with the RC4 algorithm
    40- to 128-bit programmable key
    — MDEU—message digest execution unit
    – SHA with 160- or 256-bit message digest
    – MD5 with 128-bit message digest
    – HMAC with either algorithm
    — KEU—Kasumi execution unit
    – Implements F8 algorithm for encryption and F9 algorithm for integrity checking
    – Also supports A5/3 and GEA-3 algorithms
    — RNG—random number generator
    — XOR engine for parity checking in RAID storage applications
    Dual I2C controllers
    — Two-wire interface
    — Multiple master support
    — Master or slave I2C mode support
    — On-chip digital filtering rejects spikes on the bus
    Boot sequencer
    — Optionally loads configuration data from serial ROM at reset via the I2C interface
    — Can be used to initialize configuration registers and/or memory
    — Supports extended I2C addressing mode
    — Data integrity checked with preamble signature and CRC
    DUART
    — Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
    — Programming model compatible with the original 16450 UART and the PC16550D
    Local bus controller (LBC)
    — Multiplexed 32-bit address and data bus operating at up to 133 MHz
    — Eight chip selects support eight external slaves
    — Up to eight-beat burst transfers
    — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
    — Three protocol engines available on a per chip select basis:
    – General-purpose chip select machine (GPCM)
    – Three user programmable machines (UPMs)
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