- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45368 > MPC8541ECVTAJF (FREESCALE SEMICONDUCTOR INC) 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783 PDF資料下載
參數(shù)資料
| 型號： | MPC8541ECVTAJF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 16/88頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | MPC8541ECVTAJF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.2
Freescale Semiconductor
23
Ethernet: Three-Speed, MII Management
8.2.2.1
GMII Receive AC Timing Specifications
Table 21 provides the GMII receive AC timing specifications.
Figure 7 provides the AC test load for TSEC.
Figure 7. TSEC AC Test Load
Figure 8 shows the GMII receive AC timing diagram.
Figure 8. GMII Receive AC Timing Diagram
Table 21. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period
tGRX
—8.0
—
ns
RX_CLK duty cycle
tGRXH/tGRX
40
—
60
%
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.5
—
ns
RX_CLK clock rise and fall time
tGRXR, tGRXF
2,3
——
1.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR)
with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L)
state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing
the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。