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    參數(shù)資料
    型號(hào): MPC8541ECPXAJD
    廠商: Freescale Semiconductor
    文件頁數(shù): 19/88頁
    文件大?。?/td> 0K
    描述: IC MPU POWERQUICC III 783-FCPBGA
    標(biāo)準(zhǔn)包裝: 36
    系列: MPC85xx
    處理器類型: 32-位 MPC85xx PowerQUICC III
    速度: 533MHz
    電壓: 1.2V
    安裝類型: 表面貼裝
    封裝/外殼: 783-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
    包裝: 托盤
    配用: CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
    MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
    26
    Freescale Semiconductor
    Ethernet: Three-Speed, MII Management
    8.2.3.2
    MII Receive AC Timing Specifications
    Table 23 provides the MII receive AC timing specifications.
    Figure 11 shows the MII receive AC timing diagram.
    Figure 11. MII Receive AC Timing Diagram
    Table 23. MII Receive AC Timing Specifications
    At recommended operating conditions with LVDD of 3.3 V ± 5%.
    Parameter/Condition
    Symbol 1
    Min
    Typ
    Max
    Unit
    RX_CLK clock period 10 Mbps
    tMRX
    2
    —400
    ns
    RX_CLK clock period 100 Mbps
    tMRX
    —40
    ns
    RX_CLK duty cycle
    tMRXH/tMRX
    35
    65
    %
    RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
    tMRDVKH
    10.0
    ns
    RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
    tMRDXKH
    10.0
    ns
    RX_CLK clock rise and fall time
    tMRXR, tMRXF
    2,3
    1.0
    4.0
    ns
    Notes:
    1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
    for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
    receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
    (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
    input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
    general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
    For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
    used with the appropriate letter: R (rise) or F (fall).
    2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
    3.Guaranteed by design.
    RX_CLK
    RXD[3:0]
    tMRDXKH
    tMRX
    tMRXH
    tMRXR
    tMRXF
    RX_DV
    RX_ER
    tMRDVKH
    Valid Data
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