參數(shù)資料
型號(hào): MPC8540VT833LB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 19/24頁(yè)
文件大小: 0K
描述: ICMPU 32BIT 833MHZ PPC 783FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類(lèi)型: 32-位 MPC85xx PowerQUICC III
速度: 833MHz
電壓: 1.2V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
配用: MPC8540ADS-BGA-ND - BOARD APPLICATION DEV 8540
CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
4
Freescale Semiconductor
MPC8540 Overview
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access through JTAG port
— 2.5-V SSTL2 compatible I/O
RapidIO interface unit
— 8-bit RapidIO I/O and messaging protocols
— Source-synchronous double data rate (DDR) interfaces
— Supports small type systems (small domain, 8-bit device ID)
— Supports four priority levels (ordering within a level)
— Reordering across priority levels
— Maximum data payload of 256 bytes per packet
— Packet pacing support at the physical layer
— CRC protection for packets
— Supports atomic operations increment, decrement, set, and clear
— LVDS signaling
RapidIO–compliant message unit
— One inbound data message structure (inbox)
— One outbound data message structure (outbox)
— Supports chaining and direct modes in the outbox
— Support of up to 16 packets per message
— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
— Supports one inbound doorbell message structure
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable interrupt
controller
— Four global high resolution timers/counters that can generate interrupts
— Supports 22 other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
I2C controller
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
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