參數(shù)資料
型號(hào): MPC8536ECVTAULA
廠商: Freescale Semiconductor
文件頁數(shù): 103/126頁
文件大?。?/td> 0K
描述: MPU PWRQUICC III 1333MHZ 783PBGA
產(chǎn)品培訓(xùn)模塊: MPC8536E QUICC III Processor
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8536ECVTAUL
MPC8536ECVTAUL-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
78
2.15.2
JTAG AC Electrical Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.
This table provides the JTAG AC timing specifications as defined in the following figures.
Input current
(VIN
1 = 0 V or V
IN = VDD)
IIN
—±5
μA
High-level output voltage
(OVDD = min, IOH = -2 mA)
VOH
2.4
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—0.4
V
Notes:
1. Note that the symbol VIN, in this case, represents the OVIN.
Table 58. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 3).
Parameter
Symbol 1
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
JTAG external clock cycle time
t JTG
30
ns
JTAG external clock pulse width measured at 1.4 V
tJTKHKL
15
ns
JTAG external clock rise and fall times
tJTGR & tJTGF
02
ns
TRST assert time
tTRST
25
ns
2
Input setup times:
tJTDVKH
4—
ns
Input hold times:
tJTDXKH
10
ns
Output Valid times:
tJTKLDV
—10
ns
3
Output hold times:
tJTKLDX
0—
ns
3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3.) The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
Table 57. JTAG DC Electrical Characteristics (continued)
Parameter
Symbol 1
Min
Max
Unit
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