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| 型號： | MPC8536CVTAULA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 18/126頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU PWRQUICC III 1333MHZ 783PBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.333GHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
| 其它名稱： | MPC8536CVTAUL MPC8536CVTAUL-ND |
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MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Hardware Design Considerations
Freescale Semiconductor
114
The heat sink removes most of the heat from the chip for most applications. Heat generated on the active side of the chip is
conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat
sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance
are the dominant terms.
2.24.3.2
Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is
generally provided by the thermal interface vendors.
3
Hardware Design Considerations
This section provides electrical and thermal design recommendations for successful application of the chip.
3.1
System Clocking
This chip includes seven PLLs:
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3,
The PCI PLL generates the clocking for the PCI bus
The local bus PLL generates the clock for the local bus.
There is a PLL for the SerDes1 block to be used for PCI Express interface
There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.
The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The
frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, “DDR/DDRCLK PLL Ratio.”
3.2
Power Supply Design and Sequencing
3.2.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE,
AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and
preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent
filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AVDD pins. By providing independent filters
to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783
FC-PBGA the footprint, without the inductance of vias.
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| MPC8536CVTAVL | 功能描述:微處理器 - MPU 8536 INDUSTRIAL 1500 EXT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536CVTAVLA | 功能描述:微處理器 - MPU 8536 Non E Ext Temp RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536DS | 功能描述:微處理器 - MPU MPC8536 Dev Platform RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8536E-ANDROID | 功能描述:開發(fā)板和工具包 - 其他處理器 COMEXPRESS BASED RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8536EAVTAKG | 功能描述:微處理器 - MPU PQ38S 8536 SQUID RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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