參數(shù)資料
型號： MPC8536CVTAULA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù)： 50/127頁
文件大小： 1893K
代理商： MPC8536CVTAULA
Input Clocks
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
29
2.4
Input Clocks
2.4.1
System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8536E.
2.4.2
PCI Clock Timing
When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK
input, but instead the PCI_CLK. Table 7 provides the PCI reference clock AC timing specifications for the MPC8536E.
2.4.3
Real Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2
× t
CCB, and minimum clock
low time is 2
× t
CCB. There is no minimum RTC frequency; RTC may be grounded if not needed.
Table 6. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
33
—
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
—
30
ns
—
SYSCLK rise and fall time
tKH, tKL
0.61.0
2.1ns
2
SYSCLK duty cycle
tKHK/tSYSCLK
40
—
60
%
—
SYSCLK jitter
—
+/-150
ps
3, 4
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on
SYSCLK.
Table 7. PCICLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
PCICLK frequency
fPCICLK
33
—
66
MHz
—
PCICLK cycle time
tPCICLK
15
—
30
ns
—
PCICLK rise and fall time
tKH, tKL
0.61.0
2.1ns
1
PCICLK duty cycle
tKHK/tPCICLK
40
—
60
%
—
Notes:
1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.
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