參數(shù)資料
型號: MPC8536BVTAULA
廠商: Freescale Semiconductor
文件頁數(shù): 42/126頁
文件大?。?/td> 0K
描述: MPU PWRQUICC III 1333MHZ 783PBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8536BVTAUL
MPC8536BVTAUL-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
22
2.1.2
Recommended Operating Conditions
This table provides the recommended operating conditions for this chip. Note that the values in this table are the recommended
and tested operating conditions. Proper chip operation outside these conditions is not guaranteed.
Pad power supply for SerDes transceivers and PCI Express
XVDD, X2VDD
–0.3 to 1.1
V
DDR SDRAM
Controller I/O
supply voltage
DDR2 SDRAM Interface
GVDD
–0.3 to 1.98
V
DDR3 SDRAM Interface
–0.3 to 1.65
Three-speed Ethernet I/O
LVDD (eTSEC1)
–0.3 to 3.63
–0.3 to 2.75
V2
TVDD (eTSEC3)
–0.3 to 3.63
–0.3 to 2.75
V2
PCI, DUART, system control and power management, I2C, USB,
eSDHC, eSPI and JTAG I/O voltage, MII management voltage
OVDD
–0.3 to 3.63
V
Local bus I/O voltage
BVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V—
Input voltage
DDR2/DDR3 DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
3
DDR2/DDR3 DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
Three-speed Ethernet signals
LVIN
TVIN
–0.3 to (LVDD + 0.3)
–0.3 to (TVDD + 0.3)
V3
Local bus signals
BVIN
–0.3 to (BVDD + 0.3)
PCI, DUART, SYSCLK, system control and
power management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
3
Storage temperature range
TSTG
–55 to 150
0C—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect chip reliability or cause
permanent damage to the chip.
2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V
the recommended operating conditions per protocol.
3. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7.
Table 3. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value Unit Notes
Core supply voltage
VDD_CORE
1.0 ± 50 mV
1.1 ± 55 mV
V1
Platform supply voltage
VDD_PLAT
1.0 ± 50 mV
V
PLL core supply voltage
AVDD_CORE
1.0 ± 50 mV
1.1 ± 55 mV
V1,2
PLL other supply voltage
AVDD
1.0 ± 50 mV
V
2
Table 2. Absolute Maximum Ratings1 (continued)
Characteristic
Symbol
Max Value
Unit Notes
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