參數(shù)資料
型號(hào)： MPC8535ECVTAKG
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 600 MHz, MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù)： 126/126頁
文件大?。?/td> 2861K
代理商： MPC8535ECVTAKG
PCI Express
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
99
2.21
PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8535E.
2.21.1
DC Requirements for PCI Express SD1_REF_CLK and
SD1_REF_CLK
For more information, see Section 2.20.2, “SerDes Reference Clocks.”
2.21.2
AC Requirements for PCI Express SerDes Clocks
Table 70 lists AC requirements.
2.21.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
2.21.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well
as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.
2.21.4.1
Differential Transmitter (TX) Output
Table 71 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the
component pins.
Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
tREF
REFCLK cycle time
—
10
—
ns
1
tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
——
100
ps
—
tREFPJ Phase jitter. Deviation in edge location with respect to mean edge
location
–50
—
50
ps
1,2,3
Notes:
1. Tj at BER of 10E-6 86 ps Max.
2. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 42 ps.
3. Limits from “PCI Express CEM Rev 2.0” and measured per “PCI Express Rj, D, and Bit Error Rates”.
Table 71. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Nom
Max
Units
Comments
UI
Unit Interval
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note
1.
VTX-DIFFp-p
Differential
Peak-to-Peak
Output Voltage
0.8
—
1.2
V
VTX-DIFFp-p = 2*|VTX-D+ – VTX-D-| See Note 2.
相關(guān)PDF資料
PDF描述
MPC8535EBVTANGA 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783
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