參數(shù)資料
型號: MPC8535BVTATHA
廠商: Freescale Semiconductor
文件頁數(shù): 44/126頁
文件大小: 0K
描述: MCU PWRQUICC II 1250MHZ 783-PBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.25GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8535BVTATH
MPC8535BVTATH-ND
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
24
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
Figure 7. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
The core voltage must always be provided at nominal 1.0 V . (See Table 3 for actual recommended core voltage). Voltage to the
processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3.
The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple
CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses
differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is appropriate for the
SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
B/G/L/OVDD + 20%
B/G/L/OVDD
B/G/L/OVDD + 5%
of tCLOCK
1
1. tCLOCK refers to the clock period associated with the respective interface:
VIH
VIL
Note:
2. With the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
For I2C and JTAG, tCLOCK references SYSCLK.
For DDR, tCLOCK references MCLK.
For eTSEC, tCLOCK references EC_GTX_CLK125.
For eLBC, tCLOCK references LCLK.
For PCI, tCLOCK references PCI1_CLK or SYSCLK.
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