參數(shù)資料
型號: MPC8535AVTAKG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 600 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù): 122/126頁
文件大?。?/td> 2861K
代理商: MPC8535AVTAKG
High-Speed Serial Interfaces
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
95
Figure 62 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC
levels of the clock driver chip is compatible with MPC8535E SerDes reference clock input’s DC requirement.
Figure 62. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 63 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock
driver’s common mode voltage is higher than the MPC8535E SerDes reference clock input’s allowed range (100 to 400mV),
AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-
Ω termination resistor. It also
assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external
component.
Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
CLK_Out
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVDS CLK Driver Chip
10 nF
MPC8535E
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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