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  • 參數(shù)資料
    型號: MPC8533EVTAQJB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
    文件頁數(shù): 7/116頁
    文件大?。?/td> 1277K
    代理商: MPC8533EVTAQJB
    MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
    104
    Freescale Semiconductor
    System Design Information
    Figure 62. SerDes PLL Power Supply Filter Circuit
    Note the following:
    AVDD_SRDS should be a filtered version of SVDD.
    Signals on the SerDes interface are fed from the XVDD power plane.
    21.3
    Decoupling Recommendations
    Due to large address and data buses, and high operating frequencies, the device can generate transient
    power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
    This noise must be prevented from reaching other components in the MPC8533E system, and the device
    itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
    designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin
    of the device. These decoupling capacitors should receive their power from separate VDD, TVDD, BVDD,
    OVDD, GVDD, and LVDD; and GND power planes in the PCB, utilizing short low impedance traces to
    minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.
    Others may surround the part.
    These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
    capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
    In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
    feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the
    smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
    to ensure the quick response time necessary. They should also be connected to the power and ground
    planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS
    tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
    for best values and types and quantity of bulk capacitors.
    21.4
    SerDes Block Power Supply Decoupling Recommendations
    The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low
    jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
    outlined below.
    Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
    from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
    First, the board should have at least 10
    × 10-nF SMT ceramic chip capacitors as close as possible
    to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
    directly below the chip supply and ground connections. Where the board does not have blind vias,
    2.2 F1
    0.003 F
    GND
    1.0
    Ω
    AVDD_SRDS
    Note:
    1. An 0805 sized capacitor is recommended for system initial bring-up.
    SVDD
    2.2 F1
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