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| 型號： | MPC8379CVRANGA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 70/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II 800MHZ 689PBGA |
| 標準包裝： | 27 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 800MHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 689-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 689-TEPBGA II（31x31） |
| 包裝： | 托盤 |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
56
Freescale Semiconductor
This figure provides the AC test load for the I2C.
Figure 37. I2C AC Test Load
This figure shows the AC timing diagram for the I2C bus.
Figure 38. I2C Bus AC Timing Diagram
Data hold time
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0
—
0.9
Setup time for STOP condition
tI2PVKH
0.6
—
μs—
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs—
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
—
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
—
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with
respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time.
Also, tI2PVKH symbolizes I
2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid
state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This chip provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
Table 47. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol1
Min
Max
Unit
Note
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
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