參數(shù)資料
型號(hào): MPC8378EVRAGD
廠商: Freescale Semiconductor
文件頁數(shù): 9/127頁
文件大?。?/td> 0K
描述: MPU PWRQUICC II 400MHZ 689TEPBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
106
Freescale Semiconductor
Pull Down
B16, AH18
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 k
Ω) should be placed on this pin to OVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being released to high impedance during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see
AN3665, “MPC837xE Design Checklist,” for more details.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND using a 0
Ω resistor.
8. This pin must always be left not connected.
9. For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2
Ω resistor and MDIC1 be tied to DDR
power using an 18.2
Ω resistor.
10.This pin must always be tied low. If it is left floating it may cause the device to malfunction.
11.See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
12.This pin must not be pulled down during PORESET.
13.This pin must always be tied to OVDD.
14.Open or tie to GND.
15.Voltage settings are dependent on the frequency used; see Table 3.
16.See AN3665, “MPC837xE Design Checklist,” for proper termination.
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
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