Table 16 provides the DDR capacitance" />
參數(shù)資料
型號: MPC8378CVRANGA
廠商: Freescale Semiconductor
文件頁數(shù): 39/128頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II 800MHZ 689PBGA
標(biāo)準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 800MHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
18
Freescale Semiconductor
Table 16 provides the DDR capacitance when GVDD(typ) = 2.5 V.
This table provides the current draw characteristics for MVREF.
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
This table provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.
Table 16. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT =GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 17. Current Draw Characteristics for MVREF
Parameter
Symbol
Min
Typ
Max
Unit
Note
Current draw for MVREF
DDR1
DDR2
IMVREF
250
150
600
400
Note:
1. The voltage regulator for MVREF must be able to supply up to the stated maximum current.
2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
V
Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
V
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