參數(shù)資料
型號： MPC8378CVRAGDA
廠商： Freescale Semiconductor
文件頁數(shù)： 53/128頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II 400MHZ 689PBGA
標(biāo)準(zhǔn)包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
30
Freescale Semiconductor
8.3.2
AC Requirements for SGMII L1_SD_REF_CLK and L1_SD_REF_CLK
This table lists the AC timing specifications. Note that L1_SD_REF_CLK and L1_SD_REF_CLK are not
intended to be used with, and should not be clocked by, a spread spectrum clock source.
8.3.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.3.3.1
MII Transmit AC Timing Specifications
This table provides the MII transmit AC timing specifications.
Table 30. L1_SD_REF_CLK and L1_SD_REF_CLK AC Requirements
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
L1_SD_REF_CLK/_B reference clock cycle time
100 MHz
125 MHz
tCK_REF
—
10
8
—ns
1, 2
L1_SD_REF_CLK/_B rise/fall time (80%-20%)
tCK_RISE/tCK_FALL
——
1
ns
—
L1_SD_REF_CLK/_B duty cycle (@50% L1_
nVDD)tck_dty
45%
—
55%
ps
—
L1_SD_REF_CLK/_B cycle to cycle clock jitter (period
jitter)
tCKCJ
—
100
ps
—
L1_SD_REF_CLK/_B phase jitter peak-to-peak.
Deviation in edge location with respect to mean edge
location.
tCKPJ
–50
—
50
ps
—
Notes:
1. Both options provide serial interface bit rate of 1.25 Gbps. 8 ns only applies when 125 MHz SerDes1 clock frequency is
selected during POR.
2. Tolerance of ±100 ppm.
Table 31. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—40
—
ns
TX_CLK duty cycle
tMTXH/tMTX
35
—
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
1
5
15
ns
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