參數資料
型號： MPC8377VRANGA
廠商： Freescale Semiconductor
文件頁數： 72/127頁
文件大?。?/td> 0K
描述： MPU POWERQUICC II 800MHZ 689PBGA
標準包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 800MHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應商設備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
49
11.2.2.2
Full-Speed Read Meeting Hold (Minimum Delay)
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH
Eqn. 9
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3
eSDHC AC Timing Specifications (High-Speed Mode)
This table provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and
Table 43. eSDHC AC Timing Specifications for High-Speed Mode
At recommended operating conditions OVDD = 3.3 V ± 165 mV.
Parameter
Symbol1
Min
Max
Unit
Note
SD_CLK clock frequency—high speed mode
fSHSCK
050
MHz
—
SD_CLK clock cycle
tSHSCK
20
—
ns
—
SD_CLK clock frequency—identification mode
fSIDCK
0400
KHz
—
SD_CLK clock low time
tSHSCKL
7—
ns
SD_CLK clock high time
tSHSCKH
7—
ns
SD_CLK clock rise and fall times
tSHSCKR/
tSHSCKF
—3
ns
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIVKH
5—
ns
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
tSHSIXKH
0—
ns
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSHSKHOV
—4
ns
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
tSHSKHOX
0—
ns
SD_CLK delay within device
tINT_CLK_DLY
1.5
—
ns
SD Card Input Setup
tISU
6—
ns
SD Card Input Hold
tIH
2—
ns
SD Card Output Valid
tODLY
—14
ns
SD Card Output Hold
tOH
2.5
—
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)
going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with
respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol
representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Measured at capacitive load of 40 pF.
3. For reference only, according to the SD card specifications.
4. Average, for reference only.
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