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  • 參數(shù)資料
    型號: MPC8377VRAGD
    廠商: Freescale Semiconductor
    文件頁數(shù): 110/127頁
    文件大小: 0K
    描述: MPU POWERQUICC II PRO 689-PBGA
    標準包裝: 27
    系列: MPC83xx
    處理器類型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 400MHz
    電壓: 1V
    安裝類型: 表面貼裝
    封裝/外殼: 689-BBGA 裸露焊盤
    供應商設備封裝: 689-TEPBGA II(31x31)
    包裝: 托盤
    MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
    Freescale Semiconductor
    83
    Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled)
    Figure 55. Single-Ended Reference Clock Input DC Requirements
    21.2.3
    Interfacing With Other Differential Signaling Levels
    The following list provides information about interfacing with other differential signaling levels.
    With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
    HCSL (high-speed current steering logic) compatible DC-coupled.
    Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
    be used but may need to be AC-coupled due to the limited common mode input range allowed
    (100 mV to 400 mV) for DC-coupled connection.
    LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
    clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
    addition to AC-coupling.
    SD
    n_REF_CLK
    SD
    n_REF_CLK
    Vcm
    200 mV < Input Amplitude or Differential Peak < 800 mV
    150
    Vmin > Vcm – 400m V
    fdafdVmax < Vcm + 400 mV
    Vmax < Vcm + 400 mV
    SD
    n_REF_CLK
    SD
    n_REF_CLK
    400 mV < SD
    n_REF_CLK Input Amplitude < 800 mV
    0V
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