參數(shù)資料
型號： MPC8377EWLANA
廠商： Freescale Semiconductor
文件頁數(shù)： 74/127頁
文件大?。?/td> 0K
描述： ACCESS POINT/ROUTER MPC8377
標(biāo)準(zhǔn)包裝： 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
50
Freescale Semiconductor
This figure provides the eSDHC clock input timing diagram.
Figure 29. eSDHC Clock Input Timing Diagram
11.3.1
High-Speed Output Path (Write)
This figure provides the data and command output timing diagram.
Figure 30. High Speed Output Path
11.3.1.1
High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
Zero clock delay:
tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL
Eqn. 10
With clock delay:
tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL + tCLK_DELAY
Eqn. 11
tDATA_DELAY – tCLK_DELAY < tSHSCKL – tISU – tSHSKHOV
Eqn. 12
eSDHC
tSHSCKR
External Clock
VM
tSHSCK
tSHSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode
tSHSCKL
tSHSCKH
Output valid time: tSHSKHOV
Output hold time: tSHSKHOX
tIH (2 ns)
tCLK_DELAY
Input at the
SD CLK at
Driving
Edge
Sampling
edge
the card Pin
SD card pins
tISU (6 ns)
tDATA_DELAY
tSHSCKL
tSHSCK (clock cycle)
SD CLK at the
MPC8377E pin
Output from the
MPC8377E pins
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