參數(shù)資料
型號: MPC8360VVAGDG
廠商: Freescale Semiconductor
文件頁數(shù): 53/102頁
文件大小: 0K
描述: IC MPU PWRQUICC II 740-TBGA
標(biāo)準(zhǔn)包裝: 21
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
配用: MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM
MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
54
Freescale Semiconductor
IPIC AC Timing Specifications
15.2
IPIC AC Timing Specifications
This table provides the IPIC input and output AC timing specifications.
16
SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E.
16.1
SPI DC Electrical Characteristics
This table provides the DC electrical characteristics for the device SPI.
16.2
SPI AC Timing Specifications
This table and provide the SPI input and output AC timing specifications.
Table 54. IPIC Input AC Timing Specifications1
Characteristic
Symbol2
Min
Unit
IPIC inputs—minimum pulse width
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when
working in edge triggered mode.
Table 55. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
V
Output low voltage
VOL
IOL = 6.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Input high voltage
VIH
—2.0
OVDD + 0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
0 V
≤VIN ≤OVDD
—±10
μA
Table 56. SPI AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOX
tNIKHOV
0.3
8
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOX
tNEKHOV
2
8
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
8—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4—
ns
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