參數(shù)資料
型號： MPC8360EVVALFHA
廠商： Freescale Semiconductor
文件頁數(shù)： 13/102頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 740TBGA
標準包裝： 21
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 667MHz
電壓： 1.3V
安裝類型： 表面貼裝
封裝/外殼： 740-LBGA
供應商設(shè)備封裝： 740-TBGA（37.5x37.5）
包裝： 托盤
配用： MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM
MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
18
Freescale Semiconductor
QUICC Engine Block Operating Frequency Limitations
5.3
QUICC Engine Block Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine block’s
communication interfaces.
NOTE
The settings listed below are required for correct hardware interface operation. Each
protocol by itself requires a minimal QUICC Engine block operating frequency setting for
meeting the performance target. Because the performance is a complex function of all the
QUICC Engine block settings, the user should make use of the QUICC Engine block
performance utility tool provided by Freescale to validate their system.
This table lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block core frequency for
each interface.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface of the
MPC8360E/58E.
Table 13. QUICC Engine Block Operating Frequency Limitations
Interface
Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency1 (MHz)
Notes
Ethernet Management: MDC/MDIO
10 (max)
10
20
—
MII
25 (typ)
100
50
—
RMII
50 (typ)
100
50
—
GMII/RGMII/TBI/RTBI
125 (typ)
1000
250
—
SPI (master/slave)
10 (max)
10
20
—
UCC through TDM
50 (max)
70
8
× F
MCC
25 (max)
16.67
16
× F
UTOPIA L2
50 (max)
800
2
× F
POS-PHY L2
50 (max)
800
2
× F
HDLC bus
10 (max)
10
20
—
HDLC/transparent
50 (max)
50
8/3
× F
UART/async HDLC
3.68 (max internal ref
clock)
115 (Kbps)
20
—
BISYNC
2 (max)
2
20
—
USB
48 (ref clock)
12
96
—
Notes:
1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.\
3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).
4. TDM in high-speed mode for serial data interface.
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