參數(shù)資料
型號(hào)： MPC8349CZUAGF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件頁數(shù)： 64/88頁
文件大小： 1014K
代理商： MPC8349CZUAGF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
67
Clocking
Table 53 provides the operating frequencies for the MPC8349E TBGA under recommended operating
conditions (see Table 2).
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 54 shows the multiplication factor
encodings for the system PLL.
Table 53. Operating Frequencies for TBGA
Characteristic1
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
frequency of the security core and USB modules does not exceed the respective values listed in this table.
400 MHz
533 MHz
667 MHz
Unit
e300 core frequency (
core_clk)
266–400
266–533
266–667
MHz
Coherent system bus frequency (
csb_clk)
100–266
100–333
MHz
DDR memory bus frequency (MCK)2
2 The DDR data rate is 2x the DDR memory bus frequency.
100–133
100–166.67
MHz
Local bus frequency (LCLK
n)3
3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the
csb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
166
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
166
MHz
Table 54. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication
Factor
0000
× 16
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111
× 7
1000
× 8
1001
× 9
1010
× 10
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