參數(shù)資料
    型號: MPC8347VVALF
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA672
    封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
    文件頁數(shù): 8/102頁
    文件大小: 1094K
    代理商: MPC8347VVALF
    MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
    Freescale Semiconductor
    13
    RESET Initialization
    5
    RESET Initialization
    This section describes the DC and AC electrical specifications for the reset initialization timing and
    electrical requirements of the MPC8347E.
    5.1
    RESET DC Electrical Characteristics
    Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8347E.
    5.2
    RESET AC Electrical Characteristics
    Table 9 provides the reset initialization AC timing specifications of the MPC8347E.
    Table 8. RESET Pins DC Electrical Characteristics1
    Characteristic
    Symbol
    Condition
    Min
    Max
    Unit
    Input high voltage
    VIH
    2.0
    OVDD +0.3
    V
    Input low voltage
    VIL
    –0.3
    0.8
    V
    Input current
    IIN
    ±5
    μA
    Output high voltage2
    VOH
    IOH = –8.0 mA
    2.4
    V
    Output low voltage
    VOL
    IOL = 8.0 mA
    0.5
    V
    Output low voltage
    VOL
    IOL = 3.2 mA
    0.4
    V
    Notes:
    1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
    2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
    Table 9. RESET Initialization Timing Specifications
    Parameter/Condition
    Min
    Max
    Unit
    Notes
    Required assertion time of HRESET or SRESET (input) to
    activate reset flow
    32
    tPCI_SYNC_IN
    1
    Required assertion time of PORESET with stable clock applied
    to CLKIN when the MPC8347E is in PCI host mode
    32
    tCLKIN
    2
    Required assertion time of PORESET with stable clock applied
    to PCI_SYNC_IN when the MPC8347E is in PCI agent mode
    32
    tPCI_SYNC_IN
    1
    HRESET/SRESET assertion (output)
    512
    tPCI_SYNC_IN
    1
    HRESET negation to SRESET negation (output)
    16
    tPCI_SYNC_IN
    1
    Input setup time for POR configuration signals
    (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with
    respect to negation of PORESET when the MPC8347E is in PCI
    host mode
    4—
    tCLKIN
    2
    Input setup time for POR configuration signals
    (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with
    respect to negation of PORESET when the MPC8347E is in PCI
    agent mode
    4—
    tPCI_SYNC_IN
    1
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