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| 型號(hào)： | MPC8347EZUAJDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672 |
| 封裝： | 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672 |
| 文件頁(yè)數(shù)： | 15/120頁(yè) |
| 文件大?。?/td> | 1349K |
| 代理商： | MPC8347EZUAJDA |
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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
111
System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8347EA.
21.1
System Clocking
The MPC8347EA includes two PLLs.
1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in Section 19.1, “System PLL Configuration.”
2. The e300 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 19.2, “Core PLL Configuration.”
21.2
PLL Power Supply Filtering
Each PLL gets power through independent power supply pins (AVDD1, AVDD2 respectively). The AVDD
level should always equal to VDD, and preferably these voltages are derived directly from VDD through a
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 41, one to each of the five AVDD pins.
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 41 shows the PLL power supply filter circuit.
Figure 41. PLL Power Supply Filter Circuit
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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| MPC8347EZUAJDB | 功能描述:微處理器 - MPU 8349 TBGA PB W/ ENCRYP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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