
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
115
System Design Information
Figure 43. JTAG Interface Connection
HRESET
From Target
Board Sources
HRESET
13
SRESET
NC
11
VDD_SENSE
6 1
5
15
2 k
Ω
10 k
Ω
10 k
Ω
OVDD
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP
Header
14 2
Notes:
2. Key location; pin 14 is not physically present on the COP header.
OVDD
10 k
Ω
OVDD
TRST
10 k
Ω
OVDD
10 k
Ω
10 k
Ω
CHKSTP_OUT
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pin Out
1
2
NC
PORESET
1. Some systems require power to be fed from the application board into the debugger repeater card
via the COP header. The resistor value for VDD_SENSE should be around 20
Ω .
NC