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    參數(shù)資料
    型號: MPC8343VRADDB
    廠商: Freescale Semiconductor
    文件頁數(shù): 67/80頁
    文件大?。?/td> 0K
    描述: IC MPU PWRQUICC II 620-PBGA
    產(chǎn)品培訓模塊: MPC834x PowerQUICC II Processors
    標準包裝: 36
    系列: MPC83xx
    處理器類型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 266MHz
    電壓: 1.2V
    安裝類型: 表面貼裝
    封裝/外殼: 620-BBGA 裸露焊盤
    供應商設備封裝: 620-PBGA(29x29)
    包裝: 托盤
    MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
    Freescale Semiconductor
    7
    Electrical Characteristics
    2.1.2
    Power Supply Voltage Specification
    Table 2 provides the recommended operating conditions for the MPC8343EA. Note that the values in
    Table 2 are the recommended and tested operating conditions. Proper device operation outside these
    conditions is not guaranteed.
    Input voltage
    DDR DRAM signals
    MVIN
    –0.3 to (GVDD + 0.3)
    V
    2, 5
    DDR DRAM reference
    MVREF
    –0.3 to (GVDD + 0.3)
    V
    2, 5
    Three-speed Ethernet signals
    LVIN
    –0.3 to (LVDD + 0.3)
    V
    4, 5
    Local bus, DUART, CLKIN, system control and
    power management, I2C, and JTAG signals
    OVIN
    –0.3 to (OVDD + 0.3)
    V
    3, 5
    PCI
    OVIN
    –0.3 to (OVDD + 0.3)
    V
    6
    Storage temperature range
    TSTG
    –55 to 150
    °C—
    Notes:
    1 Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
    functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
    permanent damage to the device.
    2 Caution: MV
    IN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
    power-on reset and power-down sequences.
    3 Caution: OV
    IN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
    power-on reset and power-down sequences.
    4 Caution: LV
    IN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on
    reset and power-down sequences.
    5 (M,L,O)V
    IN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
    6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
    shown in Figure 3.
    Table 2. Recommended Operating Conditions
    Parameter
    Symbol
    Recommended
    Value
    Unit
    Notes
    Core supply voltage
    VDD
    1.2 V ± 60 mV
    V
    1
    PLL supply voltage
    AVDD
    1.2 V ± 60 mV
    V
    1
    DDR and DDR2 DRAM I/O voltage
    GVDD
    2.5 V ± 125 mV
    1.8 V ± 90 mV
    V—
    Three-speed Ethernet I/O supply voltage
    LVDD1
    3.3 V ± 330 mV
    2.5 V ± 125 mV
    V—
    Three-speed Ethernet I/O supply voltage
    LVDD2
    3.3 V ± 330 mV
    2.5 V ± 125 mV
    V—
    Table 1. Absolute Maximum Ratings1 (continued)
    Parameter
    Symbol
    Max Value
    Unit
    Notes
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