參數資料
型號: MPC8343ECVRADDB
廠商: Freescale Semiconductor
文件頁數: 22/80頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 620-PBGA
產品培訓模塊: MPC834x PowerQUICC II Processors
標準包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應商設備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
29
Ethernet: Three-Speed Ethernet, MII Management
Figure 13 shows the MII management AC timing diagram.
Figure 13. MII Management Interface Timing Diagram
MDC fall time
tMDHF
10
ns
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data
timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
333 MHz, the delay is 58 ns).
Table 30. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
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