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參數(shù)資料
| 型號： | MPC8323ZQADDC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 62/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC II 516-PBGA |
| 產(chǎn)品培訓模塊： | MPC8323E PowerQUICC II Pro Processor |
| 標準包裝： | 40 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 266MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應商設備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
| 配用： | MPC8323E-RDB-ND - BOARD REFERENCE DESIGN |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
65
Clocking
22.1
Clocking in PCI Host Mode
When the MPC8323E is configured as a PCI host device (RCWH[PCIHOST] = 1), CLKIN is its primary
input clock. CLKIN feeds the PCI clock divider (
÷2) and the PCI_SYNC_OUT and PCI_CLK_OUT
multiplexors. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven
out on the PCI_SYNC_OUT signal.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system.
22.1.1
PCI Clock Outputs (PCI_CLK_OUT[0:2])
When the MPC8323E is configured as a PCI host, it provides three separate clock output signals,
PCI_CLK_OUT[0:2], for external PCI agents.
When the device comes out of reset, the PCI clock outputs are disabled and are actively driven to a steady
low state. Each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its
corresponding OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other.
22.2
Clocking in PCI Agent Mode
When the MPC8323E is configured as a PCI agent device, PCI_CLK is the primary input clock. In agent
mode, the CLKIN signal should be tied to GND, and the clock output signals, PCI_CLK_OUTn and
PCI_SYNC_OUT, are not used.
22.3
System Clock Domains
As shown in Figure 43, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create three major clock domains:
The coherent system bus clock (csb_clk)
The QUICC Engine clock (ce_clk)
The internal clock for the DDR controller (ddr_clk)
The internal clock for the local bus controller (lb_clk)
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = [PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)] × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300c2 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options. See the “Reset Configuration” section
in the MPC8323E PowerQUICC II Pro Communications Processor Reference Manual for more
information.
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| MPC8323ZQADDCA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323ZQAFDC | 功能描述:微處理器 - MPU 8323 PBGA W/O ENCR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8323ZQAFDCA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC832XE-MDS-PB | 功能描述:開發(fā)板和工具包 - 其他處理器 PROCESSOR BOARD (SOCKET) RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8343CVRADD | 功能描述:IC MPU PWRQUICC II PRO 620-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC83xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
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