參數(shù)資料
型號(hào): MPC8323CVRAFDC
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 79/82頁(yè)
文件大小: 0K
描述: IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝: 40
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA
供應(yīng)商設(shè)備封裝: 516-FPBGA(27x27)
包裝: 托盤
配用: MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
80
Freescale Semiconductor
Document Revision History
25.2
Part Marking
Parts are marked as in the example shown in Figure 46.
Figure 46. Freescale Part Marking for PBGA Devices
26 Document Revision History
Table 67 provides a revision history for this hardware specification.
Table 67. Document Revision History
Rev.
No.
Date
Substantive Change(s)
4
09/2010
Replaced all instances of “LCCR” with “LCRR” throughout.
Added footnotes 3 and 4 in Table 2, Recommended Operating Conditions3.”
Added footnote 7 and 8, and modified some signal names in Table 55, ”MPC8323E PBGA Pinout
3
12/2009
Removed references for note 4 from Table 1.
Added symbol TA in Table 2.
Added footnote 2 in Table 2.
Added a note in Section 4, “Clock Input Timing for rise/fall time of QE input pins.
Modified CLKIN, PCI_CLK rise/fall time parameters in Table 8. Modified min value of tMCK in Table 19.
Modified Figure 43.
Modified formula for ce_clk calculation in Section 22.3, “System Clock Domains.
Removed the signal ECID_TMODE_IN from Table 55.
Removed all references of RST signals from Table 55.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
PBGA
*MMMMM
YWWLAZ
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
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