RCWL[COREPLL] " />
參數(shù)資料
型號: MPC8315EVRADDA
廠商: Freescale Semiconductor
文件頁數(shù): 101/106頁
文件大小: 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
94
Freescale Semiconductor
Clocking
24.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 76 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 76 should be considered as reserved.
NOTE
Core VCO frequency = core frequency
VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 400–800 MHz.
24.3
Suggested PLL Configurations
To simplify the PLL configurations, the MPC8315E might be separated into two clock domains. The first
domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are
configured separately. Both of the domains has one common input clock. Table 77 shows suggested PLL
configurations for 33, 25, and 66 MHz input clocks.
Table 76. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider1
1 Core VCO frequency = core frequency
VCO divider.
0–1
2–5
6
nn
0000
0
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
11
nnnn
nN/A
N/A
00
0001
01:1
2
01
0001
01:1
4
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
00
0010
02:1
2
01
0010
02:1
4
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
00
0011
03:1
2
01
0011
03:1
4
Table 77. Suggested PLL Configurations
Conf. No.
SPMF
Core\PLL
Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz)
1
0100
0000100
33.33
133.33
266.66
3
0010
0000100
66.67
133.33
266.66
4
0100
0000101
33.33
133.33
333.33
5
0101
0000101
25
125
312.5
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