I2
參數(shù)資料
型號(hào): MPC8315ECVRADDA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 49/106頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤(pán)
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
47
I2C
This figure provides the test access port timing diagram.
Figure 32. Test Access Port Timing Diagram
13 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8315E.
13.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interface.
Table 47. I2C DC Electrical Characteristics
At recommended operating conditions with NVDD of 3.3 V ± 300 mv
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage level
VIH
0.7
NVDD
NVDD + 0.3
V
Input low voltage level
VIL
–0.3
0.3
NVDD
V
Low level output voltage
VOL
00.2
NVDD
V
1
High level output voltage
VOH
0.8
NVDD
NVDD + 0.3
V
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
C
B
250
ns
2
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
050
ns
3
Capacitance for each I/O pin
CI
—10
pF
Input current (0 V
V
IN NVDD)
IIN
—± 5
A4
Note:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. See the MPC8315E PowerQUICC II Pro Integrated Host Processor Family Reference Manual for information on the digital
filter used.
4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off.
VM = Midpoint Voltage (NVDD/2)
VM
tJTIVKH
tJTIXKH
JTAG
External Clock
Output Data Valid
tJTKLOX
tJTKLOZ
tJTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
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