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| 型號： | MPC8313EVRADDB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 95/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 516-PBGA |
| 標準包裝： | 40 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 267MHz |
| 電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA 裸露焊盤 |
| 供應商設備封裝： | 516-PBGAPGE（27x27） |
| 包裝： | 托盤 |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
95
24 Revision History
This table summarizes a revision history for this document.
Table 73. Document Revision History
Rev.
Number
Date
Substantive Change(s)
4
11/2011
In Table 2, added following notes:
–
Note 3: Min temperature is specified with TA; Max temperature is specified with TJ
–
Note 4: All Power rails must be connected and power applied to the MPC8313 even if the IP
interfaces are not used.
–
Note 5: All I/O pins should be interfaced with peripherals operating at same voltage level.
–
Note 6: This voltage is the input to the filter discussed in Section 22.2, “PLL Power Supply Filtering.”
and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter
Decoupled PCI_CLK and SYS_CLK_IN rise and fall times in Table 8. Relaxed maximum rise/fall time
of SYS_CLK_IN to 4ns.
Added a note in Table 27 stating “The frequency of RX_CLK should not exceed the TX_CLK by more
than 300 ppm."
In Table 30:
–
Changed max value of tskrgt in “Data to clock input skew (at receiver)” row from 2.8 to 2.6.
–
Added Note 7, stating that, “The frequency of RX_CLK should not exceed the GTX_CLK125 by
more than 300 ppm.”
Added a note stating “eTSEC should be interfaced with peripheral operating at same voltage level” in
TSEC1_MDC and TSEC_MDIO are powered at 3.3V by NVDD. Replaced LVDDA/LVDDB with NVDD
and removed instances of 2.5V at several places in Section 8.5, “Ethernet Management Interface
In Table 62:
–
Added Note 2 for LGPL4 in showing LGPL4 as open-drain.
–
Removed Note 2 from TSEC1_MDIO.
–
Added Note 10: This pin has an internal pull-up.
–
Added Note 11: This pin has an internal pull-down.
–
Added Note 12: “In MII mode, GTX_CLK should be pulled down by 300
to V
SS” to
TSEC1_GTX_CLK and TSEC2_GTX_CLK.
In Section 19.1, “Package Parameters for the MPC8313E TEPBGAII,” replaced "5.5 Sn/0.5 Cu/4 Ag"
with "Sn/3.5 Ag."
Added foot note 3 in Table 65 stating “The VCO divider needs to be set properly so that the System
PLL VCO frequency is in the range of 450–750 MHz.”
In Table 72:
–
Added AD = 266 and D = 266.
–
Added “C = 2.2” in “Revision level” column.
–
Added Note 4.
Changed resitor from 1.0
to 10 in Figure 58.
Replaced LCCR with LCRR throughout.
Added high-speed to USB Phy description.
3
01/2009
Table 72, in column aa, changed to AG = 400 MHz.
2.2
12/2008
Made cross-references active for sections, figures, and tables.
2.1
12/2008
Added Figure 2, after Table 2 and renumbered the following figures.
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