MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
33
Figure 18. SGMII AC Test/Measurement Load
8.4
eTSEC IEEE 1588 AC Specifications
This figure provides the data and command output timing diagram.
Figure 19. eTSEC IEEE 1588 Output AC Timing
This figure provides the data and command input timing diagram.
Figure 20. eTSEC IEEE 1588 Input AC Timing
This table lists the IEEE 1588 AC timing specifications.
Table 36. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
tT1588CLK
3.8
—
TRX_CLK 9ns
1, 3
TSEC_1588_CLK duty cycle
tT1588CLKH/tT1588CLK
40
50
60
%
TX
Silicon
+ Package
C = TX
R = 50
R = 50
D+ Package
Pin
D– Package
Pin
D+ Package
Pin
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
tT1588OV
tT1588CLKOUT
tT1588CLKOUTH
Note: The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is
count starting falling edge.
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
tT1588CLK
tT1588CLKH