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| 型號： | MPC8313CVRADDB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 77/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC II PRO 516-PBGA |
| 標準包裝： | 40 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 267MHz |
| 電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 516-PBGAPGE（27x27） |
| 包裝： | 托盤 |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
79
This table provides the operating frequencies for the MPC8313E TEPBGAII under recommended
operating conditions (see Table 2).
20.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. This table shows the multiplication factor
encodings for the system PLL.
Table 63. Configurable Clock Units
Unit
Default
Frequency
Options
TSEC1
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
TSEC2
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Security Core, I2C, SAP, TPR
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
USB DR
csb_clk
Off, csb_clk, csb_clk/2,
csb_clk/3
PCI and DMA complex
csb_clk
Off, csb_clk
Table 64. Operating Frequencies for TEPBGAII
Characteristic1
Maximum Operating
Frequency
Unit
e300 core frequency (core_clk)333
MHz
Coherent system bus frequency (csb_clk)167
MHz
DDR1/2 memory bus frequency (MCK)2
167
MHz
Local bus frequency (LCLKn)3
66
MHz
PCI input frequency (SYS_CLK_IN or PCI_CLK)
66
MHz
Note:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen
such that the resulting csb_clk, MCK, LCLK[0:1], and core_clk frequencies do not exceed their
respective maximum or minimum operating frequencies. The value of SCCR[ENCCM] and
SCCR[USBDRCM] must be programmed such that the maximum internal operating frequency of
the security core and USB modules do not exceed their respective value listed in this table.
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on
LCRR[CLKDIV]), which is in turn, 1x or 2x the csb_clk frequency (depending on RCWL[LBCM]).
Table 65. System PLL Multiplication Factors
RCWL[SPMF]
System PLL
Multiplication Factor
0000
Reserved
0001
Reserved
0010
2
0011
3
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