參數(shù)資料
型號: MPC8306SCVMABDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PBGA369
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁數(shù): 8/71頁
文件大?。?/td> 452K
代理商: MPC8306SCVMABDCA
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
16
Freescale Semiconductor
DDR2 SDRAM
Figure 4 shows the input timing diagram for the DDR controller.
Figure 4. DDR Input Timing Diagram
6.2.2
DDR2 SDRAM Output AC Timing Specifications
Table 16 provides the output AC timing specifications for the DDR2 SDRAM interfaces.
Table 16. DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol1
Min
Max
Unit
Notes
MCK cycle time, (MCK/MCK crossing)
tMCK
7.5
8
ns
2
ADDR/CMD output setup with respect to MCK
tDDKHAS
ns
3
266 MHz
2.5
ADDR/CMD output hold with respect to MCK
tDDKHAX
ns
3
266 MHz
2.5
MCS output setup with respect to MCK
tDDKHCS
ns
3
266 MHz
2.5
MCS output hold with respect to MCK
tDDKHCX
ns
3
266 MHz
2.5
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MDQ/MDM output setup with respect to MDQS
tDDKHDS,
tDDKLDS
ns
5
266 MHz
0.9
MDQ/MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
ps
5
266 MHz
1100
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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